BUFFER CONTROL CIRCUIT FOR MEMORY DEVICE

摘要

A buffer control circuit of a memory device is provided to minimize consumption of DRAM operation current by controlling efficiently a buffer in an auto refresh operation. A buffer control circuit of a memory device includes an auto refresh buffer control unit(20), a clock control unit(50), a command clock control unit(30), and a data input/output buffer control unit(40). The refresh buffer control unit senses a data training state in an auto refresh operation process. The clock control unit generates a clock signal(clkrp/clkfp) to be used for reading/writing data. The command clock control unit generates a clock signal to be used for a command control. The data input/output buffer control unit controls a data input/output buffer in an enable state.