发明名称 METHODOLOGY FOR REDUCING POST BURN-IN VMIN DRIFT
摘要 <p>A semiconductor device includes source/drain regions formed in a substrate (110) and having a concentration of nitrogen of at least about 5El 8 cm"3. A gate dielectric (120) is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions (140). A nitrogen-doped electrode (130) including polysilicon is located over the gate dielectric. The electrode has a concentration of nitrogen therein greater than the concentration of nitrogen in the source/drain regions.</p>
申请公布号 WO2009023694(A2) 申请公布日期 2009.02.19
申请号 WO2008US72962 申请日期 2008.08.13
申请人 TEXAS INSTRUMENTS INCORPORATED;CHAKRAVARTHI, SRINIVASAN;MEHTA, NARENDRA, SINGH;KHAMANKAR, RAJESH;VARCHESE, AJITH;BEVAN, MALCOLM, J.;GRIDER, TAD 发明人 CHAKRAVARTHI, SRINIVASAN;MEHTA, NARENDRA, SINGH;KHAMANKAR, RAJESH;VARCHESE, AJITH;BEVAN, MALCOLM, J.;GRIDER, TAD
分类号 H01L21/336 主分类号 H01L21/336
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