发明名称 PIPELINE FFT ARCHITECTURE AND METHOD
摘要 <p>Techniques for performing Fast Fourier Transforms (FFT) are described. In some aspects, calculating the Fast Fourier Transform is achieved with an apparatus having a memory (610), a Fast Fourier Transform engine (FFTe) having one or more registers (650) and a delayless pipeline (630), the FFTe configured to receive a multi-point input from the main memory (610), store the received input in at least one of the one or more registers (650), and compute either or both of a Fast Fourier Transform (FFT) and an Inverse Fast Fourier Transform (IFFT) on the input using the delayless pipeline.</p>
申请公布号 KR20090018042(A) 申请公布日期 2009.02.19
申请号 KR20087027019 申请日期 2008.11.04
申请人 QUALCOMM INCORPORATED 发明人 COUSINEAU KEVIN S.;KRISHNAMOORTHI RAGHURAMAN
分类号 H04J11/00 主分类号 H04J11/00
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