发明名称 |
Dummy pattern placement apparatus, method and program and semiconductor device |
摘要 |
The load of OPC processing (especially, the load of bias processing) has been increasing due to optical effects involved in the placement of a dummy pattern. A pattern placement apparatus places dummy patterns in a layout region where a plurality of wiring patterns is placed. The pattern placement apparatus comprises: a placement region setting section that sets a placement region, where each of the dummy patterns should be placed, in an intermediate region between the adjacent wiring patterns at substantially constant intervals to the adjacent writing patterns; and a pattern placement section that places the dummy pattern in the placement region.
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申请公布号 |
US2009049420(A1) |
申请公布日期 |
2009.02.19 |
申请号 |
US20080222600 |
申请日期 |
2008.08.12 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
KOBAYASHI NAOHIRO |
分类号 |
G06F17/50;G03F1/36;G03F1/70;H01L21/3205;H01L21/768;H01L21/82;H01L21/822;H01L23/522;H01L27/04 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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