| 摘要 |
A clock circuit with a plurality of inputs for a plurality of respective clock signals, the clock signals alternating between a first and a second state. At least one divider circuit is arranged to take an input clock signal and provide an output that is in the first state for a first fixed multiple of the duration the clock signal is in the first state, and in the second state for a second fixed multiple of the duration the clock signal is in the second state. A plurality of delay circuits are arranged to take the output of the divider circuit or circuits and provide a set of outputs each delayed by a fixed duration. A selection circuit is arranged to select the outputs of the delay circuits in sequence. The selection circuit is arranged to select the next output in the sequence at or after the time when the selected output changes from the first state to the second state. |
