| 摘要 |
The present invention is related to die bonding technology, in particular to a small- size layout for the surface areas of the planar final metal die attach pads (9) in a novel CSP-type semiconductor integrated circuit chip device assembly, wherein each planar final metal die attach pad (9) contained in this assembly layout has a surface area that is smaller in size than those of conventional semiconductor integrated circuit chips that are to be mounted on a printed circuit board's substrate in chip-scale package technology. For applications with a restricted upper tolerable limit for the total capacitance of the integrated circuit, parasitic metal-silicon capacitance, which occurs between each planar final metal die attach pad (9) and the substrate (8), is detrimental. For mechanical robust CSP products, on the other hand, it is a necessary requirement that the planar metal die attach pad area surfaces are larger in size than their associated under-bump metallization (UBM) areas (5). Reducing said parasitic metal-silicon capacitance, which can easily be achieved by using metal die attach pads (9) with smaller surface areas, is very lifetime-critical in cases where metal bonding wires (1) are required and results in that the semiconductor chip device might possibly fail during mechanical stress. A significant problem concerning the robustness of the assembly are the edges of the under-bump metallization areas (5), which is because there are usually high stress forces along these edges during the lifetime of said chip-scale packaged semiconductor chip device assembly. The present invention therefore proposes a chip-scale packaged semiconductor chip device assembly bonded onto planar final metal die attach pad layers (9) on a printed circuit board (8) by means of solder bumps, wherein the surface areas of the planar final metal die attach pad layers (9) are smaller in size than their associated under-bump metallization layers (5). For die-to-die bond wiring, very thin and hard electrically conductive materials are proposed which - according to a refinement of the present invention - may be used as surface-mounted ohmic resistors. In this case, the mechanical stability of the bump-chip connection is still given, and, at the same time, parasitic metal-silicon capacitances of the die attach pads to the substrate are reduced. |
