LOW-POWER ANALOG ARCHITECTURE FOR BRAIN-MACHINE INTERFACES
摘要
An ultra-low-power circuit for wireless neural recording and stimulation is provided. The circuit includes a neural amplifier with adaptive power biasing for use in multi-electrode arrays and a decoding and/or learning architecture. An impedance- modulation telemetry system provides low-power data telemetry. Also, the circuit includes a wireless link for efficient power transfer, and at least one circuit for wireless stimulation of neurons.
申请公布号
WO2008148097(A3)
申请公布日期
2009.02.19
申请号
WO2008US64893
申请日期
2008.05.27
申请人
MASSACHUSETTS INSTITUTE OF TECHNOLOGY;SARPESHKAR, RAHUL;RAPOPORT, BENJAMIN, I.;WATTANAPANITCH, WORADOM;MANDAL, SOUMYAJIT;ARFIN, SCOTT
发明人
SARPESHKAR, RAHUL;RAPOPORT, BENJAMIN, I.;WATTANAPANITCH, WORADOM;MANDAL, SOUMYAJIT;ARFIN, SCOTT