发明名称 MANUFACTURING METHOD OF MULTILAYER WIRING BOARD
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer wiring board in which adverse influences of plating resist residues are removed, and formation of an upper layer wiring layer and filling of a via hole are performed by electrolytic plating. <P>SOLUTION: In the manufacturing method of the multilayer wiring board wherein a prepreg 3 and metal foil 4 thereupon are laminated on a circuit-formed internal layer material 2 in one body, the via hole 5 is formed with laser after the metal foil is patterned in a hole shape, and the formation of the upper layer wiring layer and the filling of the via hole are performed through electrolytic plating, a ground electroless plating layer 7 on the upper wiring layer is etched away until the film thickness of the ground electroless plating layer 7 becomes less than a half and then the via hole 5 is filled through electrolytic filling plating 9. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009038094(A) 申请公布日期 2009.02.19
申请号 JP20070198933 申请日期 2007.07.31
申请人 HITACHI AIC INC 发明人 YOSHIDA NOBUYUKI
分类号 H05K3/46;H05K3/18;H05K3/42 主分类号 H05K3/46
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