| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the capacity of an instruction memory while suppressing the deterioration of processing performance. <P>SOLUTION: This semiconductor device 1 is provided with a plurality of arithmetic units 10A to 10E; a controller 11 for controlling a plurality of arithmetic units according to prescribed state transitions; a first storage part 12 for storing arithmetic processing object data; a second storage part for storing circuit information for designating arithmetic processing to be performed by the plurality of arithmetic units; and a third storage part for storing data access information to the first storage part 12 and a pointer to the second storage part by associating it with the state which can be acquired by the controller 11. The controller 11 reads a reading address and the pointer stored in the third storage part according to the state, and transmits circuit information stored in the region of the second storage part designated by the read pointer to the plurality of arithmetic units 10A to 10E. <P>COPYRIGHT: (C)2009,JPO&INPIT |
