| 摘要 |
A generic flexible timer design is provided to decrease an effort for realizing high quality design and to introduce a cost-down substitute when a plan error is generated. An input signal is transmitted to an input channel. A first control signal is transmitted to a first control input channel in order to control a first transmission gate. A second controlling signal is transmitted to a second control input channel in order to control the second and third transmission gates. The first, second, and third transmission gates are arranged between a first delay element and a second delay element. A pin-programmable delay cell includes a first output channel in which a first output signal is transmitted.
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