发明名称
摘要 A driving circuit for a flat panel display device includes shift register stages, each containing: a first TFT charging a Q node according to a start signal; a second TFT discharging the Q node according to an output voltage of a next shift register stage; a pull-up unit increasing an output voltage according to the Q node voltage; an odd pull-down unit decreasing the output voltage in an odd frame according to a QB-o node voltage; and an even pull-down unit decreasing the output voltage in an even frame according to a QB-e node voltage. A gate and drain of a third odd TFT connected to the QB-o node are connected to each other and receive an odd source voltage. A gate and drain of the third even TFT connected to the QB-e node are connected to each other and receive an even source voltage.
申请公布号 JP4225508(B2) 申请公布日期 2009.02.18
申请号 JP20050183225 申请日期 2005.06.23
申请人 发明人
分类号 G09G3/36;G02F1/133;G02F1/1345;G02F1/1368;G09G3/20;G11C19/00;G11C19/28 主分类号 G09G3/36
代理机构 代理人
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