MANUFACTURING METHOD OF VERTICAL CYLINDER TYPE TRANSISTOR USING DUMMY DRAIN LAYER AND VERTICAL CYLINDER TYPE TRANSISTOR MANUFACTURED BY THE SAME

摘要

A manufacturing method of vertical cylinder type transistor using dummy drain layer is provided to reduce the unit cell area and to easily control the length and the width of channel. The base substrate has with a plurality of source forming layers(13), the channel forming layer, dummy drain forming layer and the mask forming layer. A plurality of mask patterns has the mask layer and the dummy drain layer on the surface of the channel forming layer. The source electrode(21) is formed by etching the source forming layer on the board layer and is connected to the source layer(12a) of the cylinder column. The dummy space is formed by removing the dummy drain layer. The second semiconductor film is formed in the inside of the dummy space and the surface of the third silicon oxide layer(26a). A plurality of drain electrodes(28) is arranged to cross the surface of the third silicon oxide layer.