发明名称 PARALLEL BIT INTERLEAVER FOR A WIRELESS SYSTEM
摘要 Systems and methods are provided to process wireless data packets. A method includes determining a subset of data bits to be processed at a wireless transmitter and employing a clock edge to store the data. The clock edge allows parallel mapping of at least two bits from the subset of data bits into an interleaver memory per a given clock edge. From the memory, other encoding and scrambling processes are applied before transmitting the data packets across a wireless network.
申请公布号 KR20090016687(A) 申请公布日期 2009.02.17
申请号 KR20087029505 申请日期 2008.12.02
申请人 QUALCOMM INCORPORATED 发明人 BAI JINXIA;SUN THOMAS
分类号 H03M13/27;H04L1/00 主分类号 H03M13/27
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