发明名称 Hardware-error tolerant computing
摘要 Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.
申请公布号 US7493516(B2) 申请公布日期 2009.02.17
申请号 US20060364130 申请日期 2006.02.28
申请人 SEARETE LLC 发明人 FERREN BRAN;HILLIS W. DANIEL;MANGIONE-SMITH WILLIAM HENRY;MYHRVOLD NATHAN P.;TEGREENE CLARENCE T.;WOOD, JR. LOWELL L.
分类号 G06F11/00 主分类号 G06F11/00
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