| 摘要 |
A method of automatically generating planar double gate transistor shapes can include taking an integrated circuit layout design that includes single gate transistors, locating the gate shapes and active shapes for the transistors, generating top gate shapes, planar double gate active shapes, bottom gate shapes, active cavity shapes, source/drain cavity shapes, and top gate contact shapes, bottom gate contact shapes, thru-gate contact shapes, and source/drain contact shapes for the planar double gate transistors. The method can generate gate contact shapes that have top and bottom gates to be electrically connected within the same planar double gate transistor or separate gate contact shapes where the top and bottom gates are not electrically connected to each other. In one embodiment, a data processing system can include a program that has code in the form of instructions to carry out the method.
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