发明名称 |
Pattern layout and layout data generation method |
摘要 |
A transistor layout including a diffusion region and a gate line. The gate line intersects part of the diffusion region in an overlapping manner. The layout includes an L-shaped bent portion included in the diffusion region. An auxiliary pattern is included in the diffusion region opposite to the L-shaped bent portion so that the gate line is located between the L-shaped bent portion and the auxiliary pattern. The auxiliary pattern and the L-shaped bent portion are spaced from the gate line by the same distance.
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申请公布号 |
US7493582(B2) |
申请公布日期 |
2009.02.17 |
申请号 |
US20060589145 |
申请日期 |
2006.10.30 |
申请人 |
FUJITSU LIMITED |
发明人 |
KOMAKI MASAKI |
分类号 |
G06F17/50;G03F1/68;G03F1/70;H01L21/336;H01L21/82;H01L27/00;H01L29/78 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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