PHASE CHANGE MEMORY DEVICE

摘要

A phase change memory device is provided to control separately a write operation mode of a set state and a write operation mode of a reset state. A cell array unit(10) includes phase change cells which are arranged in crossing regions between word lines and bit lines(BL0-BL2). A sense amplifier(S/A) senses and amplifies data of phase change resistance cells. A write driving unit(W/D) supplies write voltages corresponding to data to be written in the cell array unit. A write verification control unit is controlled by an activation control signal(Set_con) and outputs an enable signal by comparing data read through a sense amplifier with data to be written.