发明名称 DELAY CALCULATION METHOD CAPABLE OF CALCULATING DELAY TIME WITH SMALL MARGIN OF ERROR
摘要 A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during Deltat1; and the one indicating that the voltage increases from V1 to E during Deltat2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of Deltat1, V1, and Deltat2.
申请公布号 US2009043558(A1) 申请公布日期 2009.02.12
申请号 US20080250695 申请日期 2008.10.14
申请人 RENESAS TECHNOLOGY CORP. 发明人 KOMODA MICHIO
分类号 G06F17/00 主分类号 G06F17/00
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