| 摘要 |
PROBLEM TO BE SOLVED: To provide an equalizer capable of generating a clock phase from a node by shortening a delay time of a signal in a feedback route and making the node that succeeds in equalization exist. SOLUTION: The equalizer includes: a signal determining device 3 for sequentially determining whether a data signal Sin is 0 or 1; a feedback circuit for generating a feedback signal S1_O(E) corresponding to the latest determination result by the signal determining device 3 and generating second feedback signals 2_E(O) and S3O(E) corresponding to respective past determination results from the latest determination result; and correcting parts 51(52) which is provided between a transmission path and the signal determining device 3 and have a first adder E1(O1) for correcting the data signal Sin on the basis of the second feedback signals S2_E(O) and S3O(E) and a second adder E2(O2) for correcting the data signal corrected by the first adder E1(O1) on the basis of the first feedback signal S1_O(E). COPYRIGHT: (C)2009,JPO&INPIT
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