发明名称 |
CORRECTION OF VOLTAGE OFFSET AND CLOCK OFFSET FOR SAMPLING NEAR ZERO-CROSSING POINT |
摘要 |
Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second" sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler. |
申请公布号 |
WO2008100843(A3) |
申请公布日期 |
2009.02.12 |
申请号 |
WO2008US53552 |
申请日期 |
2008.02.11 |
申请人 |
RAMBUS INC.;FULLER, ANDREW, M.;POULTON, JOHN |
发明人 |
FULLER, ANDREW, M.;POULTON, JOHN |
分类号 |
H04L25/06;H04L7/033;H04L7/04 |
主分类号 |
H04L25/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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