| 摘要 |
A decoder for decoding low density parity check coding signal is provided to perform a decoding by a minimum hardware by selecting a plurality of bit engines and check engines by a multiplexer. Each bit engine of a plurality of bit engines(931, 932) is coupled in at least one or more memory among a plurality of memories(811, 812, 813). Each check engine of a plurality of check engines(921, 922) is coupled in at least one or more memory among a plurality of memories. A plurality of multiplexers (991, 992) selectively connects a plurality of bit engines and a plurality of check engines to first selected memories for decoding processing of a first LDPC(Low Density Parity Check) coding signal. A plurality of multiplexers selectively connects a plurality of bit engines and a plurality of check engines to second selected memories for the decoding processing of a second LDPC coding signal.
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