发明名称 CLOCK MANAGEMENT BETWEEN TWO ENDPOINTS
摘要 A clock control method for managing clock between two endpoints, a clock control system, and a computer readable media are provided to synchronize a clock by shifting a reference line based on delta between packets. A transmitting device(110) transmits a first packet to a receiving device(120). The first packet is received by the receiving device and an extracted time stamp. The time stamp is used in order to set up an initial reference line. The packet is transmitted from the transmitting device to the receiving device. A clock managing module(150) determines deviation from the reference line. If delta is a negative number, the reference line is updated as amount of the negative number. If delta is a positive number, a minimum positive number delta within a present window is stored. The clock managing module determines rate of a reference line deviation about elapsed time.
申请公布号 KR20090015001(A) 申请公布日期 2009.02.11
申请号 KR20080077286 申请日期 2008.08.07
申请人 AVAYA TECHNOLOGY LLC 发明人 GIBBONS LEE D.;TUCKER LUKE A.;SCHOLTE ALEXANDER;ONG MEI SING
分类号 H04L7/02 主分类号 H04L7/02
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