发明名称 Multi-stage packet switching system with alternate traffic routing
摘要 In general, in one aspect, the disclosure describes a multi-stage switch having a plurality of ingress switching modules to receive data and to generate frames that are transmitted as a wavelength division multiplexed signal. The multi-stage switch further includes a core switching module operatively connected to receive the wavelength division multiplexed signal from the at least one ingress switch module and to switch the frames. The multi-stage switch additionally includes a plurality of egress switching modules to receive the wavelength division multiplexed signal from the core switch module and to transmit data. The multi-stage switch is capable of detecting faulty paths and transmitting data through fault-free paths.
申请公布号 US7489625(B2) 申请公布日期 2009.02.10
申请号 US20050044096 申请日期 2005.01.27
申请人 INTEL CORPORATION 发明人 VARMA ANUJAN
分类号 G01R31/08;G06F11/00;G08C15/00;H04L1/00;H04L12/26 主分类号 G01R31/08
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