| 摘要 |
A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with multi-phase reference application, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled at the common mode voltage of the input, using one or more reference capacitor(s) that has been charged in a previous clock phase to the reference feedback voltage. The sampled input voltage is then applied in series with a quantizer-controlled reference voltage to the input of an integrator in a second clock phase. The summing mode of the integrator is maintained at the reference common-mode voltage. Since the charge pulled from the input voltage source is substantially determined only by the quantization error and input noise voltage, the circuit has a high signal input impedance. Since the input voltage source is sampled with respect to its common-mode voltage, the common-mode input impedance is also high.
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