AN EFFICIENT CONSTRUCTION FOR LDPC DECODER

摘要

A LDPC decoder is provided to reduce the size of a whole hardware by performing check node calculation and variable node calculation in decoding of an LDPC(Low Density Parity Check) code. A multiplexer(40) selects one of a CNU(Check Node operation unit) and a VNU(Variable Node operation unit) according to a control signal(41). An LUT(Look Up Table,10) stores values of a function of a check node calculation performed in decoding process of an LDPC code in advance. The multiplexer is additionally inserted into the common ALU. When the control signal is 1, the multiplexer selects a signal passing through LUT. When the control signal is 0, the multiplexer selects a signal not passing through LUT.