FLASH MEMORY DEVICE IMPROVING A BIT-LINE LAYOUT STRUCTURE AND LAYOUT METHOD FOR THE SAME

摘要

A flash memory device having an improved bit-line layout structure and a layout method of the same are provided to optimize a bit-line layout structure in a DPT(Double Patterning Technology). One or more main bit lines(210) are connected to a cell string including memory cells for storing data. One or more dummy bit lines(220) are arranged in parallel to the main bit lines. A common source line(CSL) is arranged on a layer different from the layer of the bit lines including the main bit lines and the dummy bit lines. The common source line is formed to transfer a common source voltage. The dummy bit lines include a first dummy bit line for transmitting a first voltage and a second dummy bit line for transmitting a second voltage.