发明名称 METHOD FOR CONTROLLING A PIPELINE ANALOG TO DIGITAL CONVERTER AND A PIPELINE PNALOG TO DIGITAL CONVERTER IMPLEMENTING THE SAME METHOD
摘要 A control method of pipeline analog/digital converter and a pipeline analog/digital converter are provided to minimize sampling mismatch by controlling a sampling point. A pipeline analog/digital converter does not use a shear sample-and-hold amplifier. A first stage of the pipeline analog/digital converter comprises an A/D converter and a residual signal generator. The A/D converter(420) samples the analog input signal and produces first sampling value. The A/D converter amplifies the first sampling value and converses the first sampling value to corresponding digital code. The residual signal generator(410) samples an analog input signal at the same time with the sampling by the A/D converter and produces second sampling value. While the A/D converter amplifies the first sampling value, the residual signal generator holds the second sampling value. The residual signal generator produces the residual signal by using the second sampling value and digital code and delivers the generated residual signal to the second stage.
申请公布号 KR20090013312(A) 申请公布日期 2009.02.05
申请号 KR20070077314 申请日期 2007.08.01
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 JEON, YOUNG DEUK;CHO, YOUNG KYUN;KIM, KWI DONG;KWON, CHONG KI;KIM, JONG DAE;LEE, SEUNG CHUL
分类号 H03M1/12 主分类号 H03M1/12
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