| 摘要 |
PROBLEM TO BE SOLVED: To improve processing efficiency in data transfer by setting optimum access latency in the data transfer. SOLUTION: This integrated circuit has: a bus system 11 having a plurality of busses 17 connected to a bus master 14; and a memory controller 13 controlling connection between a memory 12 and the bus master 14 connected to the bus system 11. The bus system 11 has a counter 16 counting latency T (the bus master 14-the memory controller 13) until the connection between the bus master 14 and the memory controller 13 is established after making an access request Req to the memory 12 from the bus master 14, and the memory controller 13 controls access of the bus master 14 to the memory 12 based on the latency T (the bus master 14-the memory controller 13) counted by the counter 16. COPYRIGHT: (C)2009,JPO&INPIT |
