Integrated circuit for use in e.g. semiconductor device, has memory cell array with spatially positioned cavities, where size of cavities are selected such that mechanical stress occurring inside array is compensated partially by cavities

摘要

#CMT# #/CMT# The circuit has a memory cell array (300) i.e. resistive memory cell array, with a set of spatially positioned cavities (302), where size of the cavities are selected such that the mechanical stress occurring inside the memory cell array is compensated partially by the cavities. The cavities are filled with a compressible material i.e. non-porous material, or a material with a negative thermal expansion coefficient i.e. zirconium tungstate. The memory cell array has an active material layer, and the cavities are arranged within the active material layer. #CMT# : #/CMT# An independent claim is also included for a method for manufacturing an integrated circuit. #CMT#USE : #/CMT# Integrated circuit for use in memory module, semiconductor device (all claimed) and motherboard of a personal computer. #CMT#ADVANTAGE : #/CMT# The size of the cavities are selected, so that the mechanical stress occurring inside the memory cell array is compensated partially by the cavities, thus preventing delamination damages of the memory cell array when exposed to high temperatures which result from different thermal expansion coefficients, and hence resulting in more flexible production process of the memory cell array. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The drawing shows a schematic view of a portion of a memory cell array of an integrated circuit.'(Drawing includes non-English language text)' 300 : Memory cell array 302 : Cavities 303 : Bottom electrode 304 : Memory cell.