| 摘要 |
PROBLEM TO BE SOLVED: To further reduce the power consumption of a data signal delay circuit capable of delaying data signals. SOLUTION: A data signal delay circuit 100A comprises a decoder 20 which generates n pieces of enable signals E0 to En-1 which sequentially become active exclusively in synchronization with a clock signal CK, D flip-flops 30 to 3n-1 which take in and hold an input data signal Din at timing when the input data signal Din is supplied in common and the enable signals E0 to En-1 become active, and a selection unit U which generates an output data signal Dout by selecting one hold data signal corresponding to one enable signal that has become active at specified timing among n pieces of hold data signals 30a to 3n-1a taken in and held by the D flip-flops 30 to 3n-1. COPYRIGHT: (C)2009,JPO&INPIT
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