发明名称 Clock generator
摘要 A frequency divider, comprising an input for receiving an input clock signal having a first frequency; a divider, for generating an output signal having an instantaneous frequency equal to the first frequency divided by an instantaneous division ratio; and a sequence generator, for generating a sequence of instantaneous division ratios by adding a sequence of instantaneous dither values to an integer value. The instantaneous division ratios in the sequence have a mean value that is equal to an integer desired ratio, but none of the instantaneous division ratios in the sequence is equal to the integer desired ratio.
申请公布号 US2009033374(A1) 申请公布日期 2009.02.05
申请号 US20080219129 申请日期 2008.07.16
申请人 LESSO JOHN PAUL;PENNOCK JOHN LAURENCE 发明人 LESSO JOHN PAUL;PENNOCK JOHN LAURENCE
分类号 H03B21/02;H03K23/00 主分类号 H03B21/02
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