SYSTEMS AND METHODS FOR REDUCED AREA DELAY LOCKED LOOP
摘要
<p>Various systems and methods (400) for signal synchronization are disclosed. For example, some embodiments of the invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode (410) where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand (435), and the product of the multiplication is used while operating the delay lock loop circuit in a second mode (445) to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand.</p>