| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of lowering a percent defective of a memory cell and also preventing a selection transistor from being damaged. <P>SOLUTION: The semiconductor memory device is equipped with: a memory cell array 11 including a memory cell column 23 having a plurality of memory cells MC connecting one end and other ends of a current path thereto in series and a first dummy cell DMC1, a plurality of first selection transistors S1 in which one end of the current path is connected to one end of the current path of the memory cell column, and a plurality of second selection transistors S2 in which one end of the current path is connected to other ends of the current path of the memory cell column; a source line SL electrically connected to other ends of the current path of the first selection transistor; and a bit line BL electrically connected to other ends of the current path of the second selected transistor. The first dummy cell is arranged to the side of source line so that one end and other ends of the current path are connected between the first selection transistor and the memory cell, and the threshold voltage is larger than a neutral threshold voltage. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
