| 摘要 |
A word length reduction circuit comprises an input, a word length reduction block 103, a signal processing block 111 and an adder 102. The word length reduction block 103 generates an output signal and an error signal from a modified input signal, the output signal having a smaller number of bits than the modified input signal. The signal processing block 111 comprises an unstable feedback loop and receives the error signal to generate a random dither signal. The adder 102 generates the modified input signal from the input and the random dither signal. The circuit may be used in audio and video devices. |
