发明名称 CPLD for multi-wire keyboard decode with timed power control circuit
摘要 The present invention is directed to a circuit and a method that features selectively isolating a logic device from a source of power implementing a counter circuit to transmit a signal to a voltage control device to isolate a source of power from a logic device, coupled to a plurality of switching elements, with the voltage control device being coupled to allocate power to the logic device in response to activation of one of said plurality of switching elements. The logic device is typically a programmable logic device. In one embodiment, the voltage control device is a field effect transistor. In another embodiment the voltage control device is a voltage regulator.
申请公布号 US7486106(B1) 申请公布日期 2009.02.03
申请号 US20060635246 申请日期 2006.12.05
申请人 ALTERA CORPORATION 发明人 CAMAROTA RAFAEL CZERNEK
分类号 H03K17/16;H03K19/003 主分类号 H03K17/16
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