| 摘要 |
A receiver (20) for performing timing recovery over at least one complex channel at low or less than zero SNR (signal power to noise power, in dB) has at least one receive element such as an antenna, an analog-to-digital converter 21 (ADC), a fractional interpolation filter 23, a matched filter 24, and a timing correction loop 26. The timing correction loop 26 selects a minimum mean square error from the output of the matched filter 24 to determine a timing signal output to the interpolation filter 23, and provides one-bit weights to the matched filter 24. Preferably, the timing correction loop 26 includes a magnitude detector 26c, a moving average filter 26b, and a timing error detector 26a that outputs an integer m and fractional mu timing factor to the interpolation filter 23. Within a phase correction loop 27 is a maximum likelihood channel estimator 27b and a phase error detector 27a that controls a phase rotator 22 disposed between the ADC 21 and the interpolation filter 23.
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