发明名称 Methods, apparatus, and systems for flash memory bit line charging
摘要 Various embodiments include a circuit to receive data information, a memory array including memory cells coupled to a bit line, and control circuitry to charge the bit line while the data information is received at the circuit. The control circuitry may program the data information into a selected memory cell of the memory cells after the data information is received at the circuit. Other embodiments including additional methods, apparatus, and systems are disclosed.
申请公布号 US7486566(B2) 申请公布日期 2009.02.03
申请号 US20060617502 申请日期 2006.12.28
申请人 INTEL CORPORATION 发明人 HA CHANG WAN
分类号 G11C11/34;G11C16/06 主分类号 G11C11/34
代理机构 代理人
主权项
地址