| 摘要 |
<p>A manufacturing method of a semiconductor device is provided to reduce an etch target by using a conductive layer pattern during SAC etching for subsequent landing plug contact formation, thereby preventing an SAC fault with a gate and a landing plug and preventing a not-open fault of a landing plug contact. An element isolation film(11) for limiting an active area is formed in a semiconductor substrate(10). A surface height of the element isolation film is greater than a surface height of the active area. A conductive film is formed in the semiconductor substrate including the element isolation film. A planarization process is performed until the element isolation film is found. A hard mask pattern exposing a gate reserved area of the active area is formed on the conductive film and the element isolation film in which the surface is planarized. The conductive film is etched by using the hard mask pattern as an etching barrier. A conductive layer pattern(12A) is formed on the active area of both sides of the gate reserved area. An insulation spacer(14A) is formed in a side wall of the conductive layer pattern. A first gate electrode(16A) reclaimed in a space between the conductive layer patterns is formed. A second conduction film for gate electrode and a gate hard mask are formed on the overall structure of the outcome including the first gate electrode. The second conduction film for gate electrode and the gate hard mask are patterned to form a gate.</p> |
