| 摘要 |
<p>A semiconductor memory device is provided to configure a heterogeneous vertical lamination type memory device by laminating a cache memory device and a non-volatile memory device within one chip, thereby reducing a cell size and improving a data transfer rate. A gate(340) is formed on an SOI substrate(330) consisting of a silicon substrate(300), a filling oxide layer(310) and a silicon layer(320). Source /drain regions(331,332) are formed within the silicon layer of both sides of the gate. A bit line(341) is formed on the SOI substrate of the source area. And a DRAM device(381) is configured. An insulating layer(345) is formed on the DRAM device. A word line(347) is formed on the insulating layer. A PN diode(348) is formed on the word line. A bottom electrode(350) is formed on the PN diode. A lamination pattern of an upper electrode(370) and a phase changing film(360) is formed on the bottom electrode. Therefore, an PRAM device(382) is configured. A heterogeneous memory device consisting of the non-volatile memory device and the cache memory device is formed in a laminating structure within one chip.</p> |
