DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY

摘要

A power supply voltage for a memory (14) on an integrated circuit (10) is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage (VDD1). A test memory (16) of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted (30), while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory (14) and test memory (16) may be physically implemented either separated or interspersed on the integrated circuit.