HIGH VOLTAGE TRANSISTOR WITH IMPROVED HIGH SIDE PERFORMANCE AND METHOD OF MANUFACTURING THE SAME

摘要

A high voltage NMOS transistor is proposed where the p-doped body is isolated against the p-doped substrate by a DN well showing a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.