| 摘要 |
An electronic component package, includes a package substrate portion (11) constructed by a silicon substrate (10a) in which a through hole (TH) is provided, an insulating layer (14) formed on both surface sides of the silicon substrate (10a) and an inner surface of the through hole (TH), and a through electrode (18) filled in the through hole (TH), and a frame portion (23) provided upright on a peripheral portion of the package substrate portion (11) to constitute a cavity (C) on the silicon substrate (10a), wherein an upper surface of the through electrode (18) in the cavity (C) is planarized such that a height of the through electrode (18) is set equal to a height of the insulating layer (14). The frame portion (23) is joined to the package substrate portion (11) by the low-temperature joining utilizing the plasma process after the through electrode (18) is planarized. |
