发明名称 Data processing apparatus with a storage element coupled to a shared memory, which is biased against receiving new data during a transaction.
摘要 Disclosed is a multiprocessor core or multi threaded processor, consisting of logic for executing transactions, a shared memory to hold an input data element used by the transaction, a storage element coupled to the logic and the shared memory, a transaction buffer and logic to abort the transaction. The storage element is biased against receiving new data elements during the pendancy of the transaction. The transaction buffer tracks invaliding requests to the shared memory during the execution of the transaction. The transaction abort logic aborts the transaction in response to the transaction buffer tracking an invaliding request during the execution of the transaction. The apparatus may have a second storage element to hold a locking predicate value. When set to a locked value the execution logic is to execute the transaction non-speculatively using a semaphore to provide exclusive access to the data element in the shred memory. The execution logic may evaluate the count variable in response to aborting the transaction and set the locking predicate to the locking value, if the count variable represents that the transaction has been re-executed a predetermined number of times.
申请公布号 GB2451200(A) 申请公布日期 2009.01.21
申请号 GB20080018238 申请日期 2005.12.23
申请人 INTEL CORPORATION 发明人 JOHN H CRAWFORD;KUSHAGRA VAID;SAILESH KOTTAPALLI
分类号 G06F12/08;G06F9/38;G06F9/46 主分类号 G06F12/08
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