发明名称 |
CDR-based clock synthesis |
摘要 |
A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous receive and transmit clock domains of a serial data transceiver, a single common PLL is used both to recover the receive clock from the received data and to synthesize the transmit clock from a potentially noisy transmit clock source signal.
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申请公布号 |
US7480358(B2) |
申请公布日期 |
2009.01.20 |
申请号 |
US20040786879 |
申请日期 |
2004.02.25 |
申请人 |
INFINEON TECHNOLOGIES AG;RAMBUS INC |
发明人 |
PARTOVI HAMID;EVANS WILLIAM P. |
分类号 |
H04L7/00;G01R31/28;H03L7/06;H04L7/033 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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