发明名称 Method for fabricating semiconductor package with circuit side polymer layer
摘要 A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
申请公布号 US7479413(B2) 申请公布日期 2009.01.20
申请号 US20050242224 申请日期 2005.10.03
申请人 MICRON TECHNOLOGY, INC. 发明人 CONNELL MIKE;JIANG TONGBI
分类号 H01L21/00;H01L21/56;H01L21/60;H01L23/31;H01L23/495;H01L25/065 主分类号 H01L21/00
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