| 摘要 |
PROBLEM TO BE SOLVED: To provide an asynchronous circuit-verifying program data generation method, an asynchronous circuit verification method and an asynchronous circuit verification device, allowing higher-speed verification of an asynchronous circuit. SOLUTION: A clock domain straddle analysis part 111 analyzes a clock domain straddle part that is a boundary of each clock domain based on circuit data of the asynchronous circuit, and a pseudo-metastable generation circuit insertion part 113 generates circuit data wherein a pseudo-metastable generation circuit generating a signal in time of a metastable in a pseudo state is inserted in a following stage of the clock domain straddle part. An HW (Hardware) emulator part 106 operates the asynchronous circuit constructed on an FPGA (Field Programmable Gate Array) by a plurality of clock signals based on the circuit data while generating a signal in time of the metastable from the pseudo metastable generation circuit 300. Thereby, the verification of clock domain straddle can be performed at high speed. COPYRIGHT: (C)2009,JPO&INPIT
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