| 摘要 |
A semiconductor integrated circuit for generating data output clock is provided to obtain data output clock signal having the predetermined electric potential difference by authorizing the bias voltage level in data output clock signal. In a semiconductor integrated circuit, a first voltage controller outputs a first drop voltage(VR1) according to a first test mode signal(TM0) and a first fuse signal(fuse0). The second voltage controller(152) comprises a second NOR gate(NR2), a plurality of the inverter(IV3, IV4), a second passgate(TR2) and the third and fourth resistance(R3, R4). The voltage supply unit(153) is activated by the reference voltage(VCTRL), and It provides the adjusted voltage level according to the active state of the first and the second voltage controller as the first or the second bias voltage(VLOW1, VLOW2). The reference voltage generation part(154) comprises a plurality of resistances(Ra-Rd) While being connected to the external driving power source and bulk bias power source(VBB).
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