| 摘要 |
PROBLEM TO BE SOLVED: To provide an isolation technology of a semiconductor element which can reduce a chip area as compared with a prior art. SOLUTION: An N+ semiconductor layer 4, a P semiconductor layer 5, and an N+ semiconductor layer 6 are formed on the surface of the N- semiconductor layer 3. A resist layer 7 having an opening is then formed inside the N+ semiconductor layer 4 and a trench 8 for dividing the N+ semiconductor layer 4 is formed by etching a semiconductor substrate 1 selectively using the resist layer 7 as a mask. The N+ semiconductor layer 4 is divided into N+ semiconductor layers 4a and 4b. The trench 8 is then filled with an insulating film 9 such as a silicon oxide film. Thereafter, a silicon oxide film 10 having a contact hole reaching the surface of the P semiconductor layer 5 (base region), the N+ semiconductor layer 6 (emitter region), and the N+ semiconductor layers 4a, 4b (collector region) is formed. Finally, a base electrode 11, an emitter electrode 12 and a collector electrode 13 are formed in each contact hole. COPYRIGHT: (C)2009,JPO&INPIT
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