发明名称 SEMICONDUCTOR MOUNTING SUBSTRATE AND SEMICONDUCTOR PACKAGE
摘要 <P>PROBLEM TO BE SOLVED: To minimize an inductance component and to reduce noise as much as possible. <P>SOLUTION: Along the outer peripheral edge of a semiconductor chip mounting region 110 formed on the surface of a substrate, a first belt-like interconnection 12a is formed on the surface of the substrate outside the semiconductor chip mounting region 110. Along the outer peripheral edge of the first belt-like interconnection 12a, a second belt-like interconnection 13a is formed on the surface of the substrate outside the first belt-like interconnection 12a. Then, an interconnection 15a is formed contactless with the first belt-like interconnection 12a and the second belt-like interconnection 13a on the surface of the substrate. Side faces on one side of the first and second belt-like interconnections 12a and 13a are opposite to each other and are engaged with each other. In the other side face(s) of the belt-like interconnection 12a and/or the belt-like interconnection 13a, a cutout portion A is formed. The interconnection 15a is arranged in the cutout portion A. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009010187(A) 申请公布日期 2009.01.15
申请号 JP20070170484 申请日期 2007.06.28
申请人 PANASONIC CORP 发明人 YAMAGUCHI HIROSHI;URYU KAZUHIDE;YAMADA TORU
分类号 H01L23/12;H01L21/60 主分类号 H01L23/12
代理机构 代理人
主权项
地址