| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock supply circuit for switching clock signals seamlessly. <P>SOLUTION: A multiplexer 110 outputs a clock signal designated by a clock designation signal SEL, out of a plurality of supplied clock signals as a first intermediate clock CLK_M1. An inversion circuit 120 outputs the supplied first intermediate clock CLK_M1 as it is or inverts the signal level to output a second intermediate clock CLK_M2, in response to a clock inversion signal INVERT. D flip-flops 130 and 131 synchronize a stop signal STOP with a rising edge and a falling edge of the second intermediate clock CLK_M2 to generate a mask signal MASK. An AND gate 140 generates an output clock CLK_O from the second intermediate clock CLK_M2 and the mask signal MASK and outputs the output clock. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
